SRAM (static random access memory) is volatile, meaning that SRAM memory cells maintain their programmed states as long as power is supplied to the SRAM memory cell and lose their stored data when power is removed. Although SRAM memory cells typically do not need to be refreshed (i.e. data rewritten) in order to maintain their programmed states, the SRAM memory cells consume energy while maintaining their states. SRAM may be utilized in computing systems, for example, for cache memory.
Some computing systems, including, for example, battery-powered systems, embedded systems and/or systems on a chip (SOC), may be configured to transition processing elements and cache memory to a low power “sleep” state to reduce power consumption when a processor and/or processing unit is idle. In order to preserve data stored in SRAM, such data may be copied to nonvolatile storage, e.g., flash memory or hard disk drive, prior to entering the low power state. The stored data may be retrieved from the nonvolatile storage after exiting the low power state and restored to the SRAM. Thus, data may not be lost, power consumption may be reduced and energy efficiency may be improved.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.